Development and verification of FPGA IP cores in the wireless domain. Vitis Accelerator Flow. HW signal analysis. Development of projects with Xilinx RFSoC and Versal.

• Development of FPGA, SoC, and target software architecture for civil and military radar systems. • Participation in the development of information processing units during the schematic design coordination stage. • Development of digital signal processing and radar algorithms. • Implementation of DSP and radar algorithms in FPGA and SoC. • Work with SDR. • Development of synchronization systems. • Development of the logical part of the Serial RapidIO interface. • Development and implementation of active transponder algorithms. • Implementation of FPGA algorithms for meteorological radars. • Development and implementation of active interference compensation algorithms. • Development of system software for power-up and status monitoring of information processing unit hardware.