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Registration: 04.05.2023

Rodrigo R. Barrera

Portfolio

TCS Tata Consultancy Services

Part of Software Testing and Development Team as a QA Engineer I’m involved on SDLC/STLC methodologies based on pyramid tests in the development phase of manual and automated test cases to perform different requirements as functional, non-functional, regressions, patches, upgrades, performance, stress, etc. (Black Box, Grey Box and White Box). Also involved in the Defect/Bug Life Cycle to drive and track fixes problems and findings using Jira tool.

Intel

Part of automation team as a System Validation Engineer, involved in many projects based on Server and Client segment (Hardware/Software) engineering support. Implicated in the planning, definition, development, and validation phase based on Testing scenarios. Continuous improvement, driving, leading, and influencing methodologies, frameworks, and standards to following up and keeping QC/QA, enhancing the validation and Execution Testing Process on Microprocessors/SoCs according to the SLAs until meets Intel’s standards of quality and reliability in products Xeon/Atom segment.

TCS Tata Consultancy Services

Part of Software Testing and Development Team as a QA Engineer I’m involved on SDLC/STLC methodologies based on pyramid tests in the development phase of manual and automated test cases to perform different requirements as functional, non-functional, regressions, patches, upgrades, performance, stress, etc. (Black Box, Grey Box and White Box). Also involved in the Defect/Bug Life Cycle to drive and track fixes problems and findings using Jira tool.

Skills

CSS
Cucumber
Dockers
Fedora
HTML
IntelliJ
Java
Jenkins
MySQL
PHP
Postman
PyCharm
Python
RH
Selenium
Spyder
Suse
Ubuntu
VSC
Windows Server

Work experience

Sr QA Engineer
since 06.2021 - Till the present day |TCS Tata Consultancy Services
Jira
Part of Software Testing and Development Team as a QA Engineer I’m involved on SDLC/STLC methodologies based on pyramid tests in the development phase of manual and automated test cases to perform different requirements as functional, non-functional, regressions, patches, upgrades, performance, stress, etc. (Black Box, Grey Box and White Box). Also involved in the Defect/Bug Life Cycle to drive and track fixes problems and findings using Jira tool.
System Validation Engineer
11.2015 - 06.2021 |Intel
QA
Part of automation team as a System Validation Engineer, involved in many projects based on Server and Client segment (Hardware/Software) engineering support. Implicated in the planning, definition, development, and validation phase based on Testing scenarios. Continuous improvement, driving, leading, and influencing methodologies, frameworks, and standards to following up and keeping QC/QA, enhancing the validation and Execution Testing Process on Microprocessors/SoCs according to the SLAs until meets Intel’s standards of quality and reliability in products Xeon/Atom segment.

Educational background

Tecnologías de la Información
UNID
Ingeniería en Comunicaciones y Electrónica
UTEG

Languages

EnglishUpper Intermediate