Design Verification Engineer

We are looking for a Senior Design Verification Engineer to join the team with focus on verification of advanced interconnect systems in state-of-the-art microprocessors.

Work Location: Belgrade, Serbia (priority) or Bucharest, Romania.

Relocation package available.

Work Format: Hybrid possible (50% remote, 50% in-office).

Interview Process:

1. Technical screening;
2. Interview with the team.

Responsibilities:

• Perform pre-Silicon Verification of next generation high performance Microprocessor designs and related IPs;
• Develop, document and execute on verification test plans at unit level of design hierarchy;
• Develop high level language testbench components including stimulus drivers, behavioral models, monitors and checkers in SystemVerilog;
• Develop, simulate and debug directed/random stimulus to ensure design functionality according to specifications.

Requirements:

• 5+ years experience in Digital Design Verification;
• Strong skills with System Verilog and UVM;
• Good skills with Verilog;
• Exposure to both maintaining an existing Verification Environment as well as creating one from scratch;
• Experience with functional verification tools by VCS, Cadence, Mentor Graphics;
• Experience working in a Unix/Linux environment;
• Good scripting skills (Perl, Shell, Ruby);
• English B2+.

Nice to have:

• Proven experience of working with complex designs (not just I2C and other similar designs) would be an asset;
• Good computer architecture, cache coherency knowledge would be an asset;
• Exposure to simulation profile, efficiency improvement, acceleration would be an asset;
• Exposure to leadership or mentorship would be an asset.